Closed-loop clock circuits, such as phase-locked and delay-locked loops, are useful in many applications, including clock and data recovery, data retiming, clock regeneration, and other functions. Delay-locked loops are particularly useful in high-speed systems, such as high-speed memory systems.
Delay-locked loops can be used to generate clock signals, or they can be used to receive clocks signals. For example, a delay-locked loop in a first circuit may generate and provide a clock signal to a delay-locked loop in a second circuit. These delay-locked loops can clean up clock signals by removing jitter and spurious noise components. They can also retime signals to improve the performance of data transfer systems.
Various parameters or attributes can be used to describe the operating characteristics of these closed-loop clock circuits such as delay-locked loops. Loop bandwidth is one such key parameter for delay-locked loops. As loop bandwidth is increased, the resulting jitter is increased, but acquisition time, the time it takes for a delay-locked loop to lock onto an incoming clock signal, is reduced. Conversely, as loop bandwidth is decreased, the resulting jitter is decreased, but the acquisition time is increased.
It is also desirable that a delay-locked loop be able to operate over a large range of frequencies. For example, the operating frequencies of a memory or other device that includes a delay-locked loop may vary over a large range. Accordingly, it is desirable that a delay-locked loop in the memory device also be able to operate over a large range of frequencies.
If loop parameters or attributes, such as bandwidth, are kept constant as operating frequencies change, resulting parameters or attributes, such as jitter and acquisition times, will vary accordingly. It is therefore desirable to vary loop bandwidth of a delay-locked loop as its operating frequency changes.
Thus, what is needed are circuits, methods, and apparatus that allow the bandwidth of closed-loop clock circuits, such as phase-locked and delay-locked loops, to vary with changes in operating frequency.